In integrated circuit technology, devices in different integrated circuit (hereinafter referred to as "IC") packages are interconnected to one another at I/O PADS associated with each IC package. I/O PADS are associated with electrical circuits which perform a desired function to interface with other IC packages or electrical devices. An I/O PAD may be associated with electrical circuits which generate output signals and apply the signals to the I/O PAD for external devices to sense and process accordingly. Alternatively, an I/O PAD may be associated with electrical circuits which sense the logic state of signals applied to the I/O PAD by external electrical circuits or IC packages. I/O PADS are frequently "bi-directional" in the sense that they may be used at different times for the sensing of input signals to the IC package or for the application of output signals from the IC package. Electrical output signals are applied to an I/O PAD by electrical circuits within the IC package associated with the I/O PAD. Similarly, electrical input signals are received as input signals from an I/O PAD by associated electrical circuits within the IC package which "sense" the signal level and operate accordingly.
It is common for such interconnected circuits to utilize standard voltage levels to represent logic states of "0" and "1" (or "ON" and "OFF"). Common standard voltage levels in the past have been 0 Volts (.+-. a threshold value) to represent one logic state and 5 Volts (.+-. a threshold value) to represent the other logic state. As new IC manufacturing technologies evolve the voltage levels used may change. For example, in the manufacture of many current IC devices using sub-micron semiconductor fabrication processes, the semiconductor industry has begun to standardize on 3 Volt (more precisely, 3.3 Volt .+-. a threshold value) in place of 5 Volt signal levels to improve performance and reduce power dissipation. The lower voltage level permits reduced thickness in transistor gate oxide materials to thereby reduce switching time of transistor gates and improve performance of the switching circuitry.
A problem arises when such IC packages optimized for 3 Volt operation are used in conjunction with other IC packages optimized for 5 Volt operation. Transistor gates and other circuits optimized for 3 Volt operation may not withstand the application of 5 Volt signals to their I/O PADS from other interconnected IC packages. The 5 Volt signals may breakdown the thinner oxide layers of the 3 Volt optimized I/O circuits causing current leakage or even permanent destruction of the oxide layers.
It is well known to those of ordinary skill in the art to provide additional gates to protect the 3 Volt optimized circuit from the potential damage due to application of 5 Volt signals. However, the known prior designs provide such protection only when the 3 Volt circuit has source power applied. If the 3 Volt optimized circuit is powered off when a higher voltage signal is applied to one of its I/O PADS, the thinner oxide layers may still be damaged because the additional gates added for protection are non-functional without the source power. Many common applications require such protection of I/O PADS when the associated I/O circuitry is powered off.
From the above, it can be seen that there is a need for an IC I/O PAD design which protects the associated functional circuit from potential damage due to the application of excessively high voltage signals to the I/O PAD. Furthermore the protection must be operable both while the associated circuitry is powered on and while powered off.